1. Field of the Invention
This invention relates to a semiconductor device of a chip size package type and a manufacturing method thereof.
2. Description of the Related Art
CSP (Chip Size Package) has received attention in recent years as a three-dimensional mounting technology as well as a new packaging technology. The CSP means a small package having almost the same outside dimensions as those of a semiconductor die packaged in it.
Conventionally, BGA (ball grip array) type semiconductor devices have been known as a kind of CSP. In this BGA type semiconductor device, a plurality of ball-shaped conductive terminals made of metal such as solder is arrayed in a grid pattern on one surface of the package, and electrically connected with the semiconductor die mounted on the other side of the package.
When this BGA type semiconductor device is mounted on electronic equipment, the semiconductor die is electrically connected with an external circuit on a printed circuit board by compression bonding of the ball-shaped conductive terminals to wiring patterns on the printed circuit board.
Such a BGA type semiconductor device has advantages in providing a large number of conductive terminals and in reducing size over other CSP type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package), which have lead pins protruding from their sides. The BGA type semiconductor device is used as an image sensor chip for a digital camera incorporated into a mobile telephone, for example.
FIGS. 13A and 13B show an outline structure of the conventional BGA type semiconductor device. FIG. 13A is an oblique perspective figure showing a top side of the BGA type semiconductor device. FIG. 13B is an oblique perspective figure showing a back side of the BGA type semiconductor device.
A semiconductor die 104 is sealed between a first glass substrate 102 and a second glass substrate 103 through epoxy resin layers 105a and 105b in the BGA type semiconductor device 101. A plurality of conductive terminals 106 is arrayed in a grid pattern on a surface of the second glass substrate 103, that is, on the back surface of the BGA type semiconductor device 101. The conductive terminals 106 are connected to the semiconductor die 104 through a plurality of second wirings 110. The plurality of second wirings 110 is connected with aluminum wirings pulled out from inside of the semiconductor die 104, making each of the conductive terminals 106 electrically connected with the semiconductor die 104.
More detailed explanation on a cross-sectional structure of the BGA type semiconductor device 101 will be given hereafter referring to FIG. 14. FIG. 14 shows a cross-sectional view of the BGA type semiconductor devices 101 separated into individual dice along dicing lines.
A first wiring 107 is provided on an insulation film 108 on the top surface of the semiconductor die 104. The semiconductor die 104 is bonded to the first glass substrate 102 with the resin layer 105a. A back surface of the semiconductor die 104 is bonded to the second glass substrate 103 with the resin layer 105b. 
One end of the first wiring 107 is connected to the second wiring 110. The second wiring 110 extends from the end of the first wiring 107 onto a surface of the second glass substrate 103. The ball-shaped conductive terminal 106 is formed on the second wiring 110 extended onto the second glass substrate 103.
The technology mentioned above is disclosed, for example, in the Japanese Patent Application Publication No. 2002-512436.
However, there is a possibility that the first wiring 107 and the second wiring 110 are disconnected at a point of contact between them, since the area of the point of contact is very small in the BGA type semiconductor device 101 described above. Also there is a problem in step coverage of the second wiring 110.
Furthermore, the glass substrates 102 and 103 are bonded on the semiconductor die 104 through an epoxy resin in the semiconductor device described above. Since the members having different thermal expansion coefficients are thus bonded together, warping of the semiconductor wafer occurs in processes including heating treatment, thereby causing a problem of degrading work efficiency.